Semicon 2.0 sets 7nm-to-3nm chip roadmap and 100,000-design-engineer target

Electronics Minister Ashwini Vaishnaw has laid out the detailed implementation roadmap for Semicon 2.0, targeting 7nm-to-3nm chip technology within eight years and the training of 100,000 semiconductor design engineers. The plan marks a shift from fabrication-focused incentives toward a broader ecosystem spanning chip design, manufacturing equipment, materials, advanced packaging and talent.